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open fault中文是什么意思

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  • 例句与用法
  • The stuck - open faults are simulated concurrently based on iddt testing with the test pattern pairs generated above
    利用测试生成的向量对,采用瞬态电流测试方法对开路故障进行并发故障模拟。
  • And through simulative experiments by pspice , the analysis of the test results for short faults , open faults and transistor parameter errors in cmos and bicmos circuits are given
    并通过仿真实验,分析了动态电流检测方法对cmos与bicmos电路中短路故障、开路故障、晶体管参数错误的测试情况。
  • Experimental results show that more than 20 % stuck - open faults in part of is85 and iscas89 circuits can produce 2 . 5 times iddr variation , and then can be detected by iddt testing
    实验结果表明,电路中相当一部分故障是i _ ( ddt )可测的。并与以前的自动测试产生算法做了比较,此算法稳定性好、速度快且可测性测度值好。
  • In application , the test system which is established by the bst controller can test stuck - at faults , open faults and short faults on board , and gives some detail informations
    在实际应用中,利用边界扫描控制器构造的测试系统能够实现对电路板的呆滞、开路和短路故障进行有效的检测和诊断,并可提供比较详细的故障诊断信息。
  • One is hard fault , which means the stuck - open fault and the bridge fault ; another is soft fault , which refers to the component parameters going beyond the preassumed perfomance range . usually , these faults do not lead to a total failure of equipments
    一类称之为硬故障,指元件的开路和短路失效故障,另一类称之为软故障,指元件的参数超出预定的容差范围,一般它们均未使设备完全失效。
  • The stuck - open fault is simulated concurrently using iddt testing with the test pattern pairs generated above . through detaching a pattern pair into two independent patterns , the stuck - at fault are simulated concurrently . simulation results show better fault coverage . the
    最后,针对iddt测试的可行性,我们通过利用pspice软件对s208电路中的一些故障做了模拟,这些故障包括开路故障和延时故障。
  • Based on the analysis and research on fan algorithm , an iddt test pattern generation algorithm for stuck - open faults is present . in the case of ignoring hazards , for the stuck - open faults in cmos circuits , the feasibility of transient current test generation based on fan algorithm is discussed
    本文采用启发式搜索的方法,基于对fan算法的分析,在不考虑冒险的情况下对于cmos电路中的开路故障,探讨了利用fan算法进行瞬态电流测试生成的可能性。
  • There is great change of negative current component when it happens the line - open fault . it is marked as the occurrence of the fault . and it can be concluded the phase characteristic of negative current in the line . in the transient course , there are plenty of harmonics in the fault line . through the transient analysis , it is drawed that the amplitude of each harmonic in fault phase is greater than other phases . harmonic current in fault line is far greater than other normal lines
    发生断线故障以后,线路中会出现负序电流的突变,可以作为故障启动判断的标志,并且通过分析得出了故障时负序基波电流的相位特点。在故障暂态过程中,故障电流中含有大量丰富的谐波成分,各次谐波在故障期间有突变,并且衰减很快。
  • For the convenience of test , varied circuit chip defects caused by the production process are abstracted as all kinds of models . at present the commonly used fault models mainly consist of stuck - at fault , stuck - open fault , bridge fault , store fault , delay fault , etc . testing methods based on voltage testing mainly aim at stuck - at fault model and have also obtained satisfactory result in research for many years . bridge fault is tested easily by quiescent power supply current ( iddq ) testing method . in regard to stuck - open fault that is difficult to testd by quiescent power supply current ( iddq ) and voltage testing , it can is tested by the dynamic current ( iddt ) testing
    为了便于测试,我们将生产过程中集成电路出现的多种多样的缺陷抽象为各种模型。目前常用的故障模型主要有:固定故障,开路故障,桥接故障,存储故障,时滞故障等。电压测试主要针对固定型故障模型,多年的研究也取得了令人满意的结果; cmos电路中的桥接故障则宜用稳态电流测试方法( iddq )测试;对于电压和稳态电流难以测试的开路故障,可以使用瞬态电流测试( iddt )的方法进行测试。
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Last modified time:Sat, 16 Aug 2025 00:29:56 GMT

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